1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to an electrically insulating material with low dielectric constant and high mechanical strength and a method of making such an electrically insulating material.
2. Discussion of Related Art
In 1965 Gordon Moore observed that the pace of technology innovation would result in a doubling of the number of devices per unit area on an IC chip approximately every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to the schedule projected by Moore's Law for improving device density.
Maintaining such an aggressive schedule for each device generation has required continual enhancements at the corresponding technology node. Devices on a chip are typically fabricated in a substrate from semiconducting material, such as silicon, and electrically insulating material, such as silicon oxide or silicon nitride. Subsequently, the devices may be wired with electrically conducting material such as copper. The electrically conducting material may be stacked in layers that are separated vertically and horizontally by electrically insulating material.
On the one hand, the additive processes of ion implantation, annealing, oxidation, and deposition had to be improved to produce the requisite doping profiles and film stacks across the chip. On the other hand, the subtractive processes of photolithography and etch also had to be enhanced to shrink the features across the chip while maintaining pattern fidelity.
Photolithography was able to keep up with the reduction in the critical dimension (CD) needed for each device generation. However, improving the resolution that could be achieved often required compromising the depth of focus (DOF). As a result, the smaller DOF made it necessary to minimize the topography across the substrate in which the device was being formed. Planarization of the surface of the substrate with chemical-mechanical polish (CMP) became necessary to fabricate advanced devices.
In order to improve device density, both the transistor in the front-end of semiconductor processing and the wiring in the back-end of semiconductor processing have to be scaled down. The scaling of the transistor and the scaling of the wiring must be carefully balanced to avoid degrading performance or reliability of the chip.
The switching speed of the transistor may be adversely impacted by an excessively large resistance-capacitance (RC) product delay in the wiring. Resistance in the wiring may be reduced by using electrically conducting material with low resistivity. Capacitance in the wiring may be reduced by using electrically insulating material with low dielectric constant (k).
However, the electrically insulating material with low dielectric constant must also have high mechanical strength to withstand the rigors of front-end and back-end of semiconductor processing, as well as, the packaging steps.
Thus, what is needed is an electrically insulating material with low dielectric constant and high mechanical strength and a method of making such an electrically insulating material.